The present invention is directed to memory devices and more particularly to testing of memory cells.
FIG. 1 illustrates a cross sectional view of a conventional flash memory transistor, also known as a flash memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2 schematically illustrates a conventional NAND type flash memory array 200 that includes flash memory transistors, each of which can be implemented by the flash memory transistor depicted in FIG. 1. A string Ki (where i can be any number) includes a selection transistor Tixe2x88x921, memory transistors Mixe2x88x921 to Mixe2x88x92j (where j can be any number), and a selection transistor Tixe2x88x922, all being serially coupled. String Ki can be coupled to a bit line Bi and a common source CS through selection transistors Tixe2x88x921 and Tixe2x88x922, respectively. The control gates for selection transistors Tixe2x88x921 and Tixe2x88x922 are respectively connected to selection lines Sl1 and Sl2. The control gates for the memory transistors Mixe2x88x921 to Mixe2x88x92j are respectively connected to word lines W1 to Wj.
A flash memory transistor represents logical LOW (a logic state) when it is programmed, i.e., having a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits (e.g., 0.5 V). A memory transistor represents a logical HIGH (also a logic state) when it is erased, i.e., having a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits (e.g., xe2x88x920.7 V).
A memory transistor connected to a word line can be programmed to represent logical LOW by applying a programming voltage (e.g., 16 V to 20 V) to the word line and applying a ground to the source, the drain, and the well of the memory transistor. The programming voltage causes charge to deposit on the floating gate FG of the memory transistor through the Fowler-Nordheim (xe2x80x9cFNxe2x80x9d) tunneling phenomenon, thereby raising its threshold voltage. Conversely, a memory transistor connected to a word line can be erased to represent logical HIGH by applying a ground to the word line and applying an erase voltage (e.g., 19 to 20 V) to the well of the memory transistor. The drain and source junctions will couple up to the well potential minus a diode drop (e.g., 18.3 to 19.3 V). The erase voltage causes charge to be removed from the floating gate of the memory transistor through the FN tunneling phenomenon, thereby lowering its threshold voltage. The threshold voltage of a logical HIGH bit is hereinafter referred to as xe2x80x9cerase Vtxe2x80x9d.
A flash memory transistor connected to a selected word line and a selected bit line can be read by applying a voltage to the selection transistors (e.g., 4 V), unselected word lines (e.g., 4 V), and a ground to the selected word line and the common source. A current is allowed to flow in the bit line during the evaluation period. If the bit line potential increases above the trip-point of a sensing circuit (e.g., a data-latch in combination with a cascode device), the memory transistor is read as a logical LOW. If the bit line potential stays below the trip-point of the sensing circuitry, then the memory transistor is read as a logical HIGH.
The market for flash memory devices demands manufacturers to guarantee a data retention rate for their products (e.g., data retention for 10 years at 85xc2x0 C.). Unfortunately, a memory transistor erased to represent a logical HIGH bit can collect charge on its floating gate under normal operations over time, thereby gaining a higher threshold voltage. This memory transistor will corrupt the stored data if its threshold voltage shifts high enough to be read as a logical LOW bit. To prevent data corruption, the manufacturers can use a large read margin, i.e., a large difference in threshold voltages, between logical LOW and logical HIGH bits. A large read margin can prevent data corruption by allowing erased memory transistors to gain slightly higher threshold voltages over time without being read as logical LOW bits. However, process variations can cause a small number of memory transistors to perform poorly over a relatively short period of time. These memory transistors can gain higher threshold voltages too quickly under normal operations and thereby corrupting the stored data prior to the end of the manufacturers"" guarantee.
Accordingly, there is a need for a method and an apparatus that determines erase Vt""s of memory transistors and the changes in erase Vt""s of memory transistors to identify unusable memory transistors.
The present invention provides a method and an apparatus that determine erase Vt""s of erased flash memory transistors. The present invention also provides a method and an apparatus that identify erased memory transistors with poor data retention characteristics using the erase Vt""s. In accordance with one embodiment of the present invention, a voltage Vbias is applied to the common source and gradually increased until a logical HIGH bit is read as a logical LOW bit. If a memory transistor is read as a logical HIGH bit while Vbias is applied to the common source, i.e., if the memory transistor conducts a current, then the erase Vt of that memory transistor is less than xe2x88x92Vbias. If a memory transistor is read as a logical LOW bit while Vbias is applied, i.e., if the memory transistor does not conduct, then the erase Vt of that memory transistor is greater than xe2x88x92Vbias. Thus, by iteratively increasing Vbias, the erase Vt of each memory transistor can be determined. Once the erase Vt of each flash memory transistor in a flash memory device is determined, the flash memory device can be put under stress tests to simulate normal operative conditions. After the stress tests, the erase Vt of each memory transistor can be once again determined to ascertain the change in the erase Vt (i.e., the data retention characteristic, of each memory transistor).